1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Background Art
Hitherto, an LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) has been frequently used in a power integrated circuit. The LDMOS is a semiconductor device capable of switching heavy current.
FIG. 8 is a circuit diagram showing a general DC-DC converter using an LDMOS. This DC-DC converter employs a synchronous back converter. The current source of high voltage Vcc is connected to the drain electrode of an LDMOS 1, and a ground GND is connected to a source electrode of an LDMOS 2. A current is supplied from a node N between the LDMOSs 1 and 2 to a load via a filter.
An input signal is supplied to a gate electrode of each of the LDMOSs 1 and 2 from a control circuit. The control circuit controls an input IN1 of the LDMOS 1 and an input IN2 of the LDMOS 2 so that the LDMOSs 1 and 2 are not in the ON state simultaneously.
When the LDMOS 1 is ON, current is supplied from the current source of the voltage Vcc to the load. Due to existence of an inductance L, when the LDMOS 1 changes from the ON state to the OFF state, regenerative current flows from the ground GND to the load via a Shottky barrier diode SBD as shown by the arrow in FIG. 8. It can prevent the potential of the drain of the LDMOS 2 from becoming lower than the potential of the ground to a certain extent.
On the other hand, when a high voltage is applied to the drain of the LDMOS 2, the Schottky barrier diode SBD does not act. The operation of the LDMOS 2 in this case will be described later with reference to FIG. 9.
FIG. 9 is an enlarged sectional view of the LDMOS 2. The LDMOS 2 includes a P-type silicon substrate 910, an N−-type semiconductor layer 920, a P-type semiconductor layer 930, a P-type buried layer 940, an N-type buried layer 950, a P-type connection region 960, and an N-type connection region 970.
Multiple P-type base layers 980, N+-type source layers 982, N+-type drain layers 986, and N−-type field relaxation layers 984 are formed in the surface region of the semiconductor layer 930. Further, a gate electrode, a source electrode, and a drain electrode are formed on the surface of the semiconductor layer 930.
The operation of the LDMOS 2 in the case where a high voltage is applied to the drain electrode will be described. When a high voltage is applied to the drain electrode, a depletion layer extends from a junction between the field relaxation layers 984 and the base layers 980 or a junction between the field relaxation layers 984 and semiconductor layer 930. When the depletion layer reaches the drain layers 986, avalanche breakdown occurs at an end of the drain layers 986. By the avalanche breakdown, electrons move into the drain layers 986 and holes move into the base layers 980 or buried layers 940.
The N+-type drain layers 986, P-type semiconductor layer 930, and N-type buried layer 950 construct a parasitic NPN bipolar transistor BPT. Since the semiconductor layer 930 acts as the base of the parasitic bipolar transistor BPT, when holes move into the semiconductor layer 930, the parasitic bipolar transistor BPT can be activated.
When a high voltage is applied to the drain electrode, the depletion layer extends also to the semiconductor layer 930. It makes the semiconductor layer 930 seemingly thinner. Since the semiconductor layer 930 acts as the base of the parasitic bipolar transistor BPT, reduction in the seeming thickness of the semiconductor layer 930 corresponds to reduction in the width of the base of the parasitic bipolar transistor BPT. As a result, the gain of the parasitic bipolar transistor BPT increases, so that the parasitic bipolar transistor BPT is activated more easily.
In this case, since the Schottky diode SBD shown in FIG. 8 does not operate, when the parasitic bipolar transistor BPT is activated, a large unavailable current flows from the drain to the ground. The unavailable current represents a waste of power.
The P-type buried layer 940 can prevent activation of the parasitic bipolar transistor BPT to a certain extent in the case where a high voltage is applied to the drain electrode. Since impurity concentration of the P-type buried layer 940 is higher than that of the semiconductor layer 930, the base resistance is lowered. Therefore, an effect of decreasing the gain of the parasitic bipolar transistor BPT is produced. As a result, it reduces the tendency of activation of the parasitic bipolar transistor BPT. The buried layer 940 is electrically connected to the buried layer 950 by a short-circuit plug. Therefore, the holes generated by the avalanche breakdown are discharged from the buried layer 940 to the ground GND via the connection region 960. As a result, a potential difference between the buried layers 940 and 950 can be decreased, and it reduces the tendency of activation of the parasitic bipolar transistor BPT.
However, since the connection region 960 is formed around the LDMOS 2, the distance of drifting of holes in the buried layer 940 is long. Particularly, the drift distance of holes moved from the center portion of the LDMOS 2 is longer as compared with that of holes moved from the peripheral portion. When the drift distance of holes is long, the potential difference occurs between the buried layers 940 and 950 at distance from the peripheral part. As a result, the parasitic bipolar transistor BPT is activated. Particular, when the device area of the LDMOS 2 is large, the drift distance of holes becomes long, so that the possibility that the parasitic bipolar transistor BPT is activated increases.
To make the parasitic bipolar transistor BPT inactive, there is a method of short-circuiting the drain layer 986 and the buried layer 950 by omitting the buried layer 940 and the connection region 960 and connecting the drain electrode to the short-circuit plug without connecting the source electrode to the short-circuit plug. However, when the potential of the drain becomes lower than that of the source, a diode constructed by the silicon substrate 910 and the buried layer 950 is biased in the forward direction. It makes current flow to the silicon substrate 910. The current flowing in the silicon substrate 910 is called a substrate current, which exerts an adverse influence on peripheral logic circuits in the semiconductor chip such as the control circuit shown in FIG. 1.
Therefore, a semiconductor device with reduced unavailable current and suppressed substrate current is desired.